The invention is in the field of interval timers, as for microprocessor systems, for example, the microprocessor system sold by MOS Technology, Inc., of Pennsylvania under the generic designation 650X. One typical purpose of an interval timer in such microprocessor systems is to provide an interrupt request to the microprocessor at the expiration of a selected time interval measured by counting a selected number of pulses of the microprocessor system clock. A typical use of an interval timer is to assist an input/output device in periodically sending an interrupt request to the microprocessor, this interrupt request if honored by the microprocessor resulting, for example, in a routine for servicing the input/output device. For flexibility, it must be possible to conveniently change the length of the interval measured by an interval timer. In the prior art known to the inventor, this is done, for example, by loading a countdown register via the data bus of the microprocessor system with a number equal to the number of system clock pulses which must be counted before an interrupt request should issue, and then issuing an interrupt request when the register counts down to zero. It can be appreciated that if the register is to be loaded in one step with an initial number to configure the interval timer, and the interval is to have a sufficiently wide range, the countdown register must be large and it must be accessed by a correspondingly large number of data lines. One common technique known to the inventor is to use a 16-bit countdown register accessed in one load operation by 16 data lines. This, of course, can be done only in microprocessor systems using 16-bit data buses. In microprocessor systems using 8-bit data buses it has been common to use two 8-bit countdown registers and to load them for configuring the interval timer via the same 8-bit bus but in different loading cycles. This, of course, means a delay in configuring an interval timer.
The invention herein provides an interval timer which has a wide interval range and can be configured with a single load operation, and yet needs a relatively low number of data lines and otherwise optimizes chip layout and reduces the number of control lines needed to access timer functions. In a specific illustration of the invention, the interval timer includes an 8-bit programmable countdown register which can be loaded with an 8-bit number via data bus in a single load operation. A prescale divide-down register is interposed between the microprocessor system clock and the programmable countdown register. The prescale register is capable of dividing the system clock by one of several selected factors which are powers of two, e.g., noncontiguous powers of two, such as the factors 1, 8, 64 and 1,024. One of the several possible dividing factors of the prescale register is selected via lines of the address bus, for example, by the two lowest order address bus lines.
In operation, an 8-bit number is loaded into the programmable countdown register via the 8-bit data bus, and at the same time one of the divide factors of the prescale register is selected via the two lowest order address bus lines. This is done in a single load operation. Then the prescale register provides an output pulse with each input clock pulse if the divide factor one has been selected, or provides an output pulse for each 8 clock pulses if the divide factor of 8 has been selected, etc. Each time the prescale register provides an output pulse, i.e., at each prescale time period, the programmable countdown register is decremented by one. When the programmable register counts down through zero, it provides an output pulse which sets an interrupt flag, and the interrupt flag, if not disabled by the microprocessor, provides an interrupt request to the microprocessor.
One advantage of an interval timer in accordance with the invention is that the timer can be configured in a single load operation, thereby avoiding loss of valuable microprocessor time as compared to interval timers having 8-bit buses and using two load cycles. Another advantage is a saving in IC chip layout area while retaining wide timing interval range, because only a relatively low number of bus lines are needed to configure the interval timer (e.g., 8 data bus lines and 2 address bus lines as compared to 16 lines in a prior art interval timer using a 16-bit data bus and a 16-stage countdown register). Stated differently, the interval timer in accordance with the invention reduces the number of control lines needed to access timer functions while saving chip area and minimizing data bus loading.